HLASM - BR = Branch Register

The opcode of the BR extended mnemonic is X'07' with mask B'1111'.

The mask is the third hex digit of the instruction, and - though this is uncommon - can be regarded as the third hex digit of the opcode as well.


  1. Perform an unconditional branch.


  1. Register holding the destination address.


  1. The processor uses the PSW's two-bit condition code as an index into the 4-bit condition mask.
  2. The selected mask-bit is always one, so it branches to the address specified in the second argument.
  3. The condition code does not change.

Special Cases

  1. If the destination address is in register 0 no branch will be taken; instead the CPU will perform a serialization and checkpoint function.

Related Instructions

  1. B branches to a location that is directly addressable in base-displacement form.
  2. BCR is the real instruction associated with this extended mnemonic.


  1. All hardware supports the BR instruction.


  1. The PSW's Amode setting determines how many bits are used for the destination address.


         YREGS                          * Define register names
         XR    R15,R15                  * Set returncode = 0
         BR    R14                      * Return to caller

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