HLASM - BCR = Branch on Condition Register

The opcode of the BCR instruction is X'07'.


This instruction implements the IF function by conditionally skipping a part of the program's logic. Alternatively it can be used to build a loop by branching back.

  1. Conditionally branch forward to skip some logic.
  2. Conditionally branch backward to repeat some logic.


  1. 4-bit condition mask (in the instruction).
  2. Register holding the destination address.


  1. The processor uses the PSW's two-bit condition code as an index into the 4-bit condition mask.
  2. If the selected mask-bit is one, then it branches to the address specified in the second argument. If the bit is zero, then the processor continues with the next instruction.
  3. The condition code does not change.

Special Cases

  1. If the destination address is in register 0 no branch will be taken.
  2. If the destination address is in register 0 AND the mask is B'1111' then no branch will be taken but a serialization function will be performed instead.

Overview of rules, regarding condition mask and register number

  Mask = B'0000' B'0000' < Mask < B'1111' Mask = B'1111'
R0 Never branch nowhere Maybe branch nowhere Always branch nowhere
(Serialize + Checkpoint)
R1-R15 Never branch somewhere Maybe branch somewhere Always branch somewhere

Related Instructions

  1. BC branches to a location that is directly addressable in base-displacement form.
  2. BCTR is intended for building loops.
  3. BASR and BALR both expect a return tby means of a BCR instruction.


  1. All hardware supports the BCR instruction.


  1. The PSW's Amode setting determines how many bits are used for the destination address.
  2. HLASM supports various so-called extended mnemonics that have an implied mask value. For an overview please refer to the list of extended mnemonics for BCR.
  3. Some instructions will alter the condition code in the PSW, some won't. When a BCR instruction tests the condition code, it may have been set by the preceding instruction, or it may have remained unchanged during the execution of the last few instructions. Thus, it is possible that the condition code was set quite a few instructions before being tested by the current BCR instruction.


         YREGS                          * Define register names
         BCR   B'1000',R5               * Branch in case....
         BCR   B'1111',R14              * Return to caller

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