HLASM - BCTR = Branch on CounT Register

The opcode of the BCTR instruction is X'06'.


The BCTR instruction is intended for use at the end of a loop. That is, before starting the loop the number of iterations over the loop is set up in the count register. At the end of each pass over the loop the count is decremented and the loop is repeated until the count drops to zero.

  1. Decrement a counter to loop a specified number of times.
  2. Decrement a counter or length value.


  1. Register holding the current count.
  2. Register holding the destination address.


  1. The processor decrements the first register, which holds a count.
  2. Normally, the processor branches to the destination address, but if the count has just dropped to zero, then it continues with the next instruction.
  3. The condition code does not change.

Special Cases

  1. If the destination address is in register 0, no branch will be taken after decrementing the count, even if the count did go to zero.

Related Instructions

  1. BCT loops to an address that is directly addressable in base-displacement form.
  2. BCTGR uses a 64-bit counter.
  3. BCTG uses a 64-bit counter and loops to an address that is directly addressable in base-displacement form.


  1. All hardware supports the BCTR instruction.


  1. The PSW's Amode setting determines how many bits are used for the destination address.


         YREGS                          * Define register names
SETUP    LA    R2,12                    * Repeat 12 times
         LA    R3,LOOP                  * Start point of loop
         ...                            * More initialization
LOOP     EQU   *                        * Start of loop
         ...                            * Content of the loop goes here
         BCTR  R2,R3                    * Repeat until count drops to 0

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