HLASM - BCT = Branch on CounT

The opcode of the BCT instruction is X'46'.


The BCT instruction is intended for use at the end of a loop. That is, before starting the loop the number of iterations over the loop is set up in the count register. At the end of each pass over the loop the count is decremented and the loop is repeated until the count drops to zero.

  1. Decrement a counter to loop a specified number of times.


  1. Register holding the current count.
  2. Destination address (index, base, displacement) where loop is to be resumed if count is not yet zero.


  1. The processor decrements the register, which holds a count.
  2. Normally, the processor branches to the destination address, but if the count has just dropped to zero, then it continues with the next instruction.
  3. The condition code does not change.

Special Cases

  1. None.

Related Instructions

  1. BCTR loops to an address that is contained in a register.
  2. BCTGR uses a 64-bit counter and loops to an address that is contained in a register.
  3. BCTG uses a 64-bit counter.


  1. All hardware supports the BCT instruction.


  1. The PSW's Amode setting determines how many bits are used for the destination address.


         YREGS                          * Define register names
SETUP    LA    R2,12                    * Repeat 12 times
LOOP     EQU   *                        * Start of loop
         ...                            * Content of the loop goes here
         BCT   R2,LOOP                  * Repeat until count drops to 0

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