HLASM - BHR = Branch on High Register

The opcode of the BHR extended mnemonic is X'07' with mask B'0010'.

The mask is the third hex digit of the instruction, and - though this is uncommon - can be regarded as the third hex digit of the opcode as well.


  1. Perform a branch if the condition code is 2 or B'10', meaning "high".
  2. Condition code 2 may occur after compare operations, such as CLC, indicating the first operand was higher than the second.


  1. Register holding the destination address.


  1. The processor uses the PSW's two-bit condition code as an index into the 4-bit condition mask.
  2. If the selected mask-bit is one, then it branches to the address specified in the second argument. If the bit is zero, then the processor continues with the next instruction.
  3. The condition code does not change.

Special Cases

  1. If the destination address is in register 0 no branch will be taken.

Related Instructions

  1. BPR is a synonym for the BHR mnemonic.
  2. BH branches to a location that is directly addressable in base-displacement form.
  3. BCR is the real instruction associated with this extended mnemonic.


  1. All hardware supports the BHR instruction.


  1. The PSW's Amode setting determines how many bits are used for the destination address.


         YREGS                          * Define register names
         CR    R6,R1                    * Check for max.
         BHR   R14                      * Max. exceeded: return

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