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The table below lists all documented order codes for instruction SIGP (SIGnal Processor)
Remark:
Please note that the creation of descriptions for all individual
instructions
is an ongoing process. As yet no such descriptions have been created
for
the opcodes on this page.
All instructions in this table are four bytes in length. The first byte always has a value of X'AE'. The order code is taken from the second-operand address. Hence it is not part of the assembled instruction's object code. This order code designates the exact pseudo opcode.
| SIGP AE |
_0 | _1 | _2 | _3 | _4 | _5 | _6 | _7 | _8 | _9 | _A | _B | _C | _D | _E | _F |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0_ | SENS | EC | ES | STRT | STOP | RSTRT | SASTS | ICR | CR | SPFX | STSA | |||||
| 1_ | STESA | SA | CES | SENSRS | SMT | STASA | ||||||||||
| 2_ | ||||||||||||||||
| 3_ | ||||||||||||||||
| 4_ | ||||||||||||||||
| 5_ | ||||||||||||||||
| 6_ | ||||||||||||||||
| 7_ | ||||||||||||||||
| 8_ | ||||||||||||||||
| 9_ | ||||||||||||||||
| A_ | ||||||||||||||||
| B_ | ||||||||||||||||
| C_ | ||||||||||||||||
| D_ | ||||||||||||||||
| E_ | ||||||||||||||||
| F_ |
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