High Level Assembler - Opcodes overview, Halfword Immediate Extension Set A5

The tables below list all documented opcodes in extension set A5 for IBM mainframe processors. Each opcode links to a text section with some additional info on the pertinent opcode.

The first table lists all opcodes in the current extension set A5. These are all Halfword-Immediate operations. Older versions of the architecture supported a different extension set A5, which was used for Vector-Facility instructions. These are in the second table.

Opcode Assignments.

Remark:
Please note that the creation of descriptions for all individual instructions is an ongoing process. As yet no such descriptions have been created for the opcodes on this page.

Extension Set A5 - Halfword Immediate

All instructions in this table are four bytes in length. The first byte always has a value of X'A5', the second half of the second byte designates the exact instruction.

A5	0	1	2	3	4	5	6	7	8	9	A	B	C	D	E	F
	IIHH	IIHL	IILH	IILL	NIHH	NIHL	NILH	NILL	OIHH	OIHL	OILH	OILL	LLIHH	LLIHL	LLILH	LLILL

Extension Set A5 - Vector Facility

All instructions in this table are four bytes in length. The first byte always has a value of X'A5', the second byte designates the exact instruction.

All entries in this table have a slightly darker background because the entire extension set is no longer supported on either current mainframe hardware or by IBM's current version of HLASM. The associated mnemonics are printed in italics.

A5	_0	_1	_2	_3	_4	_5	_6	_7	_8	_9	_A	_B
0_	VAER	VSER	VMER	VDER			VMCER	VACER	VCER	VLER VLR	VLMER VLMR	VLZER VLZR
1_	VADR	VSDR	VMDR	VDDR			VMCDR	VACDR	VCDR	VLDR	VLMDR	VLZDR
2_	VAR	VSR	VMR		VNR	VOR	VXR		VCR
3_
4_	VLPER	VLNER	VLCER	VSQER
5_	VLPDR	VLNDR	VLCDR	VSQDR
6_	VLPR	VLNR	VLCR
7_
8_	VAEQ	VSEQ	VMEQ	VDEQ	VMAEQ	VMSEQ			VCEQ	VLEQ	VLMEQ
9_	VADQ	VSDQ	VMDQ	VDDQ	VMADQ	VMSDQ			VCDQ	VLDQ	VLMDQ
A_	VAQ	VSQ	VMQ		VNQ	VOQ	VXQ		VCQ	VLQ	VLMQ
B_
C_
D_
E_
F_

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To the Halfword-Immediate instructions.
To the Vector Facility instructions.

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