High Level Assembler - Opcodes overview, Extension Set E0

The table below lists all documented opcodes in extension set for IBM mainframe processors. Each opcode links to a text section with some additional info on the pertinent opcode.

Opcode Assignments.

Please note that the creation of descriptions for all individual instructions is an ongoing process. As yet no such descriptions have been created for the opcodes on this page.

Extension Set E0 - Assist

The Assist feature was developed by a University. Its purpose was to avoid the complexities of I/O programming during classes. The operations defined for the Assist feature were assigned to unused opcodes, and the assembler they used was modified to support these non-existent opcodes. Of course the generated load modules could not be run on real mainframe hardware. In stead they were emulated. I do not know whether the emulator ran on different hardware, or on a mainframe with an ESTAE (exception handling) routine that would intercept the unavoidable S0C1-Abends.

All entries in this table have a slightly darker background because the entire extension set is - and newver was - supported either on mainframe hardware or by IBM's version of HLASM. The associated mnemonics are printed in italics.

All instructions in this table are probably six bytes in length. The first byte always has a value of X'E0'. The second byte has a value in the range X'00' through X'0F' and designates the exact instruction.

E0 0 1 2 3 4 5 6 7 8 9 A B C D E F


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