The table below lists all documented opcodes in extension set B2 for IBM mainframe processors. Each opcode links to a text section with some additional info on the pertinent opcode.
Please note that the creation of descriptions for all individual instructions is an ongoing process. As yet no such descriptions have been created for the opcodes on this page.
All instructions in this table are four bytes in length. The first byte always has a value of X'B2', the second byte designates the exact instruction.
Entries with a slightly darker background are no longer supported
on current mainframe hardware and/or not supported by IBM's current
of HLASM. The associated mnemonics are printed in italics.
Opcodes that have no (known) mnemonic assigned to them are denoted by their hexadecimal opcode; these are explained below the table.
Information on millicode-only instructions is very limited. What you find here has been gleaned from various IBM patents. Some of these patents appear to contain some errors, or maybe even intentional obfuscation. For example, the instructions RFLG and SFLG seem to have the same opcodes as STFPC and LFPC respectively. Strange, or maybe even suspicious.
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